UH
J
ꢌꢀD
GGUꢀꢀ
0
3
%
7ꢁ
ꢉꢁ
ꢁ
ꢀꢀ
Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
%
$ꢂ
ꢀꢀ
%
$ꢀꢁ
ꢀꢀ
$ꢂꢃ
ꢀꢀ
$ꢂ
ꢂ
ꢀꢀꢀ
$
ꢂ
ꢁ
ꢀꢀ $
ꢈ
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$
ꢇ
ꢀꢀ
$
ꢆ
ꢀꢀ
$ꢄ
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$
ꢊ
ꢀꢀ
$
ꢉ
ꢀꢀ
$
ꢅ
ꢀꢀ
$ꢃ
ꢀꢀ
$
ꢂ
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$
ꢁ
ꢀꢀ
ꢁꢀꢀ
ꢂꢀꢀ
ꢂꢀꢀ
TABLE 9
EMR(3) Programming Extended Mode Register Definition (BA[1:0]=10B)
Description
Bank Adress[1]
Field
Bits
Type1)
BA1
14
1B
BA1 Bank Address
BA0
A
13
Bank Adress[0]
1B
BA0 Bank Address
[12:0]
w
Address Bus[12:0]
0B
A[12:0] Address bits
1) w = write only
TABLE 10
ODT Truth Table
Input Pin
EMRS(1) Address Bit A10
EMRS(1) Address Bit A11
x16 components
DQ[7:0]
DQ[15:8]
LDQS
X
X
X
0
LDQS
X
X
UDQS
X
0
UDQS
LDM
X
X
UDM
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
Rev. 1.43, 2006-11
14
03292006-L40N-L04G
QIMONDA [ QIMONDA AG ]
