Internet Data Sheet
HYB18T2G[40/80]2BF
2-Gbit Dual Die Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Data Mask ×4/ ×8 Organizations
F3 DM
I
SSTL
Data Mask
Note: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH coincident with that input data during
a write access. DM is sampled on both edges of DQS. Although
DM balls are input only, the DM loading matches the DQ and DQS
loading. For ×8 components the data mask function is disabled, if
RDQS/RDQS are enabled by EMRS(1) command.
Power Supplies ×4×8 Organizations
G1, G3, E9, G7, VDDQ
PWR
–
I/O Driver Power Supply
G9
E1, R1, J9, M9 VDD
PWR
PWR
–
–
Power Supply
F2, H2, E7, F8, VSSQ
I/O Driver Power Supply
H8
E3, J3, N1, P9 VSS
PWR
Al
–
–
–
–
Power Supply
J2
J1
J7
VREF
VDDL
VSSDL
I/O Reference Voltage
Power Supply
PWR
PWR
Power Supply
Not Connected ×4 Organization
E2, F1, H1, H9, NC
R3, R7, F9, A1,
A2, A8, A9, W1,
W2, W8, W9
NC
–
Not Connected
Note: No internal electrical connection is present
Not Connected ×8 Organization
R3, R7, A1, A2, NC
A8, A9, W1,
NC
–
Not Connected
W2, W8, W9
Other Balls ×4 / ×8 Organizations
K9
N9
ODT0
ODT1
I
I
SSTL
SSTL
On-Die Termination Control
Note: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is applied to each DQ,
DQS, DQS and DM signal for ×4 and DQ, DQS, DQS, RDQS,
RDQS and DM for ×8 configurations. OTD0 is the on-die
termination signal for the lower die and OTD1 for the upper die in
the dual-die package
Rev. 1.10, 2007-11
8
10192006-0E3U-5BSU
Date: 2007-11-05
QIMONDA [ QIMONDA AG ]
