Internet Data Sheet
HYB18T2G[40/80]2BF
2-Gbit Dual Die Double-Data-Rate-Two SDRAM
TABLE 1
Performance Table
QAG Speed Code
–2.5
–3S
–3.7
–5
Unit
DRAM Speed Grade
CAS-RCD-RP latencies
DDR2
–800E
6–6–6
–667D
5–5–5
–533C
4–4–4
–400B
3–3–3
tCK
Max. Clock Frequency CL3
CL4
fCK3
fCK4
fCK5
fCK6
tRCD
tRP
200
266
333
400
15
200
266
333
–
200
266
266
–
200
200
–
MHz
MHz
MHz
MHz
ns
CL5
CL6
–
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
15
15
15
15
40
55
15
15
15
ns
tRAS
tRC
45
45
45
ns
60
60
60
ns
1.2
Description
The 2-Gbit DDR2 DRAM consists of two 1-Gbit Double Data-
Rate-Two dies in one package. Each 1-Gbit device is
organized as 32 Mbit ×4 I/O ×8 banks or 16 Mbit ×8 I/O ×8
banks chip.
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 17 bit address bus for ×4 and ×8 organised components is
used to convey row, column and bank address information in
a RAS-CAS multiplexing style.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1 for performance figures.
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
Since dual-die components share the same DQ bus, each of
the two 1-Gbit dies can be individually selected by its own CS,
CKE and ODT signal. All other signals are common for both
dies.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
The DDR2 SDRAM is available in TFBGA package.
Rev. 1.10, 2007-11
4
10192006-0E3U-5BSU
Date: 2007-11-05
QIMONDA [ QIMONDA AG ]
