Internet Data Sheet
HYB18T2G[40/80]2BF
2-Gbit Dual Die Double-Data-Rate-Two SDRAM
2
Configuration
This chapter contains the chip configuration.
2.1
Configuration for FBGA-71
The chip configuration of a DDR2 SDRAM is listed by function in Table 3. The abbreviations used in the Ball# Type columns
are explained in Table 4 and Table 5 respectively. The ball numbering for the FBGA package is depicted in Figure 1 for ×4,
Figure 2 for ×8.
TABLE 3
Configuration
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×4/×8 Organizations
J8
CK
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
K8
K2
M1
CK
CKE0
CKE1
Control Signals ×4/×8 Organizations
K7
L7
K3
L8
L9
RAS
CAS
WE
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
CS0
CS1
Chip Select
Address Signals ×4/×8 Organizations
L2
L3
L1
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Rev. 1.10, 2007-11
6
10192006-0E3U-5BSU
Date: 2007-11-05
QIMONDA [ QIMONDA AG ]
