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G
G
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Zꢀ
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Zꢀ
Zꢀ
0
3
%
7ꢁ
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HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Functional Description
Table 8
Field
BT
Mode Register Definition (BA[2:0] = 000B)
Bits Type1)
Description
Burst Type
3
w
0B
1B
BT, Sequential
BT, Interleaved
BL
[2:0]
w
Burst Length
Note:All other bit combinations are illegal.
010B BL, 4
011B BL, 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by
tCK (in ns) and rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to
fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by
tCK.MIN
.
%
$
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$
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$
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$
ꢅꢀ
$
ꢊꢀ
$
ꢉꢀ
$
ꢈꢀ
/ꢀ
$
ꢂꢀ
$
ꢄꢀ
$
ꢃꢀ
$
ꢁꢀ
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2
ꢀ
3U
R
J
U
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ꢁꢀ
4ꢀ I 5'
4
6ꢀ '4
6
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$
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ꢁꢀ
ꢃꢀ
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Table 9
Field
BA2
Extended Mode Register Definition (BA[2:0] = 001B)
Bits Type1)
Description
16
reg. addr.
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B BA2, Bank Address
Bank Address [1]
BA1
BA0
15
14
0B
BA1, Bank Address
Bank Address [0]
0B
BA0, Bank Address
Internet Data Sheet
16
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
