UH
JꢌꢀD
GGUꢀ
0
3
%
7ꢁ
ꢂꢇꢄꢀ
HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Functional Description
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ꢃꢀ %
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ꢃ
ꢂꢀ $
ꢃ
ꢄꢀ $
ꢃꢃ
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ꢃ
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$ꢊꢀ
$
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$ꢄꢀ
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ꢃꢀ
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6
5
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Table 10
Field Bits
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B)
Type1)
Description
reg.addr Bank Address[2]
Note:BA2 is not available on 256Mbit and 512Mbit components
0B BA2, Bank Address
Bank Adress[1]
BA2
16
BA1
BA0
A
15
1B
BA1, Bank Address
14
Bank Adress[0]
0B
BA0, Bank Address
[13:8]
w
w
Address Bus[13:8]
Note:A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B A[13:8], Address bits
Address Bus[7]
SRF
[7]
Note:When DRAM is operated at 85 °C ≤ TCASE < 95 °C the extended self refresh rate
must be enabled by setting bit A7 to "1" before the self refresh mode can be
entered.
0B
1B
A7, disable
A7, enable, adapted self refresh rate for TCASE > 85 °C
A
[6:0]
w
Address Bus[6:0]
0B A[6:0], Address bits
1) w = write only
Internet Data Sheet
18
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
