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0337
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HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Pin Configuration
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Figure 2
Pin Configuration for ×8 components, PG-TFBGA-68 (top view)
Note:RDQS / RDQS are enabled by EMRS(1)
command.
2. When enabled, RDQS & RDQS are used as strobe
signals during reads.
3. VDDL and VSSDL are power and ground for the DLL.
1. If RDQS / RDQS is enabled, the DM function is
disabled
V
V
DDL is connected to VDD on the device. VDD, VDDQ
SSDL, VSS, and VSSQ are isolated on the device.
,
Internet Data Sheet
12
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
