UH
JꢌꢀD
GGUꢀ
0
3
%
7ꢁ
ꢈꢁꢁꢀ
HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Functional Description
%
$
ꢄꢀ %
$
ꢃꢀ %
$
ꢁꢀ $
ꢃ
ꢂꢀ $
ꢃ
ꢄꢀ $
ꢃꢃ
ꢀ $
ꢃ
ꢁꢀ
$
ꢇꢀ
$
ꢆꢀ
$
ꢅꢀ
ꢁꢀ
$ꢊꢀ
$
ꢉꢀ
$
ꢈꢀ
$
ꢂꢀ
$ꢄꢀ
$
ꢃꢀ
$ꢁꢀ
ꢁꢀ
ꢃꢀ
ꢃꢀ
Table 11
Field
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B)
Bits Type1)
Description
BA2
16
reg.addr
Bank Address[2]
Note:BA2 is not available on 256Mbit and 512Mbit components
0B
BA2, Bank Address
BA1
BA0
A
15
14
Bank Adress[1]
1B
BA1, Bank Address
Bank Adress[0]
1B
BA0, Bank Address
[13:0] w
Address Bus[13:0]
Note:A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B A[13:0], Address bits
1) w = write only
Internet Data Sheet
19
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
