HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.8
Data Termination Disable (DTERDIS)
The Data Termination Disable command is detected by
the device by snooping the bus for Read commands
when CS is high. The terminators are disabled starting
at CL - 1 clocks after the DTERDIS command is
detected and the duration is 4 clocks. The command
and address terminators are always enabled.
CLK#
CLK
CKE
DTERDIS may only be applied to the GDDR3 Graphics
memory if it is not in the Power Down or in the Self
Refresh state.
CS#
RAS#
The timing relationship between DTERDIS and other
commands is defined by the constraint to avoid
contention on the RDQS bus (i.e Read to DTERDIS
transistion) or the necessity to have a defined
termination on the data bus during Write (i.e. Write to
DTERDIS transition). ACT and PRE/PREALL may be
applied at any time before or after a DTERDIS
command.
CAS#
WE#
A2-A7, A9
A0, A1
A10-A11
A8
AP: AutoPrecharge
Don't Care
BA0-BA2
Figure 45 Data Terminal Disable Command
0
1
2
3
6
7
8
9
10
11
CLK#
CLK
Com.
Addr.
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
CAS latency = 7
DQ
Termination
Data Terminations are disabled
DTD:
Com.: Command
Addr.: Address B / C
DTERDIS
Don't Care
N/D : NOP or Deselec
Figure 46 DTERDIS Timing
Data Sheet
64
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
