HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.7.5
Read followed by DTERDIS
0
1
2
3
6
7
8
9
10
12
13
14
15
16
CLK#
CLK
Com.
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
DTD
Addr. B/Cx
CAS latency = 7
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
0
1
2
3
6
7
8
9
10
13
14
15
16
17
CLK#
CLK
Com.
RD
N/D
N/D
N/D
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr. B/Cx
CAS latency = 7
RDQS
DQ
Dx0 Dx1 Dx2 Dx3
B / Cx: Bank / Column address x
RD:
READ
Don't Care
Dx#:
Data from B / Cx
DTD: DTERDIS
DES: Deselect
DQs : Terminations off
RDQS : Not driven
Com.: Command
Addr.: Address B / C
N/D: NOP or Deselect
Figure 41 Read Command followed by DTERDIS
1. At least 3 NOPs are required between a READ command and a DTERDIS command in order to avoid
contention on the RDQS bus in a 2 rank system.
2. CAS Latency 7 is used as an example.
3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4
clocks.
4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command
corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case,
RDQS would be driven by the second Graphics DRAM.
Data Sheet
60
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
