HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.8.1
DTERDIS followed by DTERDIS
0
1
2
3
6
7
8
9
10
11
12
13
14
15
CLK#
CLK
Com.
Addr.
DTD
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
CAS latency = 7
RDQS
DQ
0
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK#
CLK
Com.
Addr.
DTD
N/D
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
CAS latency = 7
RDQS
DQ
Com.
Addr.
DTD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
CAS latency = 7
RDQS
DQ
Com.: Command
B / Cx: Bank / Column address x
Don't Care
Addr.: Address B / C
RD:
READ
DTD: DTERDIS
DQs : Terminations off
RDQS : Not driven
N/D :
Dx#:
NOP or Deselect
Data from B / Cx
Figure 47 DTERDIS Command followed by DTERDIS
1. At least 1NOP is required between 2 DTERDIS commands. This correspond to a Read to Read transistion on
the other memory in a 2 rank system.
2. CAS Latency 7 is used as an example.
3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4
clocks.
4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command
corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case,
RDQS would be driven by the second Graphics DRAM.
Data Sheet
65
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
