HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.8.3
DTERDIS followed by Write
0
1
2
3
6
7
8
9
10
11
12
13
CLK#
CLK
Com.
Addr.
DTD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
B/Cw
CAS latency = 7
Write latency = 3
WDQS
DQ
D0w D1w D2w D3w
DTD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
B/Cw
Write latency = 4
CAS latency = 8
WDQS
DQ
D0w D1w D2w
B / Cw: Bank / Column address for WRITE
WR: WRITE
DTD: DTERDIS
DES: Deselect
Dxw: WRITE Data from B / C
Com.: Command
Addr.: Address B / C
Don't Care
DQs : Terminations off
Figure 49 DTERDIS Command followed by Write
1. Write shown with nominal value of tDQSS
.
2. WDQS can only transition when data is applied at the chip input and during pre- and postambles
3. The minimum distance between DTERDIS and Write is (CL - WL + BL/2 +2) clocks.
Data Sheet
67
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
