P93U422
FUNCTIONALDESCRIPTION
An active LOW write enable (WE) controls the writing/
reading operation of the memory. When chip select one
(CS1)and writeenable(WE)areLOWand chipselecttwo
(CS2) is HIGH, the information on data inputs (D0 through
D3) is written into the addressed memory word and
preconditions the output circuitry so that true data is
present at the outputs when the write cycle is complete.
This preconditioning operation insures minimum write
recovery times by eliminating the “write recovery glitch.”
Readingisperformedwithchipselctone (CS1)LOW, chip
select two (CS2) HIGH, write enable (WE) HIGH and
output enable (OE) LOW. The information stored in the
addressed word is read out on the noninverting outputs
(O0 through O3). The outputs of the memory go to an
inactive high impedance state whenever chip select one
(CS1) is HIGH, or during the write operation when write
enable (WE) is LOW.
TRUTHTABLE
Mode
CS2 CS1 WE OE
Output
High Z
High Z
High Z
DOUT
Notes: H = HIGH
Standby
Standby
DOUTDisabled
Read
L
X
H
L
X
X
X
H
L
X
X
H
L
L = Low
X = Don't Care
X
H
H
H
HIGH Z = Implies outputs are disabled or off. This
condition is defined as high impedance state
for the P93U422.
L
L
Write
X
High Z
SWITCHINGCHARACTERISTICS(5,6)
Over Operating Range (Commercial and Military)
P93U422
Description
Delay from Address to Output (Address Access Time) (See Fig. 2)
Unit
Parameters
Max.
Min.
(7)
tPLH(A)
tPLH(A)
35
ns
ns
(7)
tPZH (CS1, CS2)(8)
25
25
25
Delay from Chip Select to Active Output and Correct Data (See Fig. 2)
tPZL (CS1, CS2)(8)
tPZH (WE)(8)
tPZL (WE)(8)
Delay from Write Enable to Active Output and Correct Data (Write Recovery)
(See Fig. 1)
ns
ns
tPZH (OE)(8)
Delay from Output Enable to Active Output and Correct Data (See Fig. 2)
tPZL (OE)(8)
ns
ns
ns
ns
ns
ns
ns
tS(A)
Setup Time Address (Prior to Initiation of Write) (See Fig. 1)
Hold Time Address (After Termination of Write) (See Fig. 1)
Setup Time Data Input (Prior to Initiation of Write) (See Fig. 1)
Hold Time Data Input (After Termination of Write) (See Fig. 1)
Setup Time Chip Select (Prior to Initiation of Write) (See Fig. 1)
Hold Time Chip Select (After Termination of Write) (See Fig. 1)
5
5
5
5
5
5
th(A)
tS(DI)
th(DI)
tS (CS1, CS2)
th (CS1, CS2)
tpw(WE)
20
Minimum Write Enable Pulse Width (to Insure Write) (See Fig. 1)
tPHZ (CS1, CS2)(8)
30
Delay from Chip Select to Inactive Output (HIGH Z) (See Fig. 2)
ns
tPLZ (CS1, CS2)(8)
tPHZ (WE)(8)
tPLZ (WE)(8)
Delay from Write Enable to Inactive Output (HIGH Z) (See Fig. 1)
Delay from Output Enable to Inactive Output (HIGH Z) (See Fig. 2)
30
30
ns
ns
tPHZ (OE)(8)
tPLZ (OE)(8)
Document # SRAM102 REV A
Page 3 of 10
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