P1750AE/SOS
1,2 (continued)
SIGNAL PROPAGATION DELAYS
20 MHz
25 MHz
30 MHz
Min Max
Min
Max
38
34
34
44
44
44
60
50
Min
Max
Symbol
tFC(IBD)V
tC(SNW)
Parameter
Unit
IB0-IB15
SNEW
34
30
30
40
40
40
55
45
32
28
28
38
38
38
52
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TRIGO RST
DMA enable
DMA enable
tFC(TGO)
tRSTL(DMA ENL)
tC(DME)
Normal power up
tFC(NPU)
tC(ER)
Clock to major error unrecoverable
RESET
tRSTL(NPU)
tREQV(C)
tC(REQ)X
tFV(BB)H
tBBH(F)X
tIRV(C)
Console request
0
15
5
0
15
5
0
15
5
Console request
Level sensitive faults
Level sensitive faults
IOL1-2INT user interrupt (0-5) setup
5
5
5
0
0
0
Power down interrupt level sensitive
hold
tC(IR)X
15
25
15
25
15
20
ns
Reset pulse width
ns
ns
ns
ns
t
RSTL (tRSTH)
Clock to three-state
Edge sensitiive pulse width
Clock rise and fall
24
5
20
4
18
3
tC(XX)Z
5
5
5
tf(F), t1(1)
tr, tf
Notes
1. 4.5V ≤ V
≤ 5.5V, –55°C ≤ T ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
C
CC
2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third
in parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "C" or the falling edge "FC" is
referenced. When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" -
valid, "Z" - high impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
3. Functional test shal consist of the same functional test patterns used when testing the equivalent standard CMOS SMD 5962-87665
processor.
Do c um e nt # MICRO-7 REV B
Pa g e 7 o f 22
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
