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PCS5P23Z09DG-16-TR 参数 Datasheet PDF下载

PCS5P23Z09DG-16-TR图片预览
型号: PCS5P23Z09DG-16-TR
PDF下载: 下载PDF文件 查看货源
内容描述: 多路输出时序- SAFE™峰值EMI降低IC [Multiple Output Timing-Safe™ Peak EMI reduction IC]
分类和应用:
文件页数/大小: 14 页 / 657 K
品牌: PULSECORE [ PulseCore Semiconductor ]
 浏览型号PCS5P23Z09DG-16-TR的Datasheet PDF文件第2页浏览型号PCS5P23Z09DG-16-TR的Datasheet PDF文件第3页浏览型号PCS5P23Z09DG-16-TR的Datasheet PDF文件第4页浏览型号PCS5P23Z09DG-16-TR的Datasheet PDF文件第5页浏览型号PCS5P23Z09DG-16-TR的Datasheet PDF文件第7页浏览型号PCS5P23Z09DG-16-TR的Datasheet PDF文件第8页浏览型号PCS5P23Z09DG-16-TR的Datasheet PDF文件第9页浏览型号PCS5P23Z09DG-16-TR的Datasheet PDF文件第10页  
PCS5P23Z05D  
PCS5P23Z09D  
May 2007  
rev0.2  
Electrical Characteristics for PCS5P23Z05D and PCS5P23Z09D  
Parameter  
Description  
Input LOW Voltage1  
Input HIGH Voltage1  
Input LOW Current  
Input HIGH Current  
Output LOW Voltage2  
Output HIGH Voltage2  
Supply Current  
Test Conditions  
Min  
Typ  
Max  
0.8  
Unit  
V
VIL  
VIH  
IIL  
2.0  
V
VIN = 0V  
50  
100  
0.4  
µA  
µA  
V
IIH  
VIN = VDD  
VOL  
VOH  
IDD  
Zo  
IOL = 8mA  
IOH = -8mA  
2.4  
V
Unloaded outputs at 150MHz  
60  
mA  
Output Impedance  
23  
Notes:  
1. REF input has a threshold voltage of VDD/2  
2. Parameter is guaranteed by design and characterization. Not 100% tested in production  
Switching Characteristics for PCS5P23Z05D and PCS5P23Z09D  
Parameter  
Description  
Output Frequency  
Test Conditions  
Min  
100  
Typ  
Max  
150  
60  
Unit  
MHz  
%
1/t1  
10pF load  
Duty Cycle2 = (t2 / t1) * 100 Measured at 1.4V  
40  
50  
t3  
t4  
t5  
Output Rise Time1,2  
Output Fall Time 1,2  
Measured between 0.8V and 2.0V  
2.50  
2.50  
250  
nS  
Measured between 2.0V and 0.8V  
All outputs equally loaded  
nS  
Output-to-output skew 2  
Delay, REF Rising Edge to  
CLKOUT Rising Edge 2  
pS  
t6  
Measured at VDD /2  
0
0
±350  
pS  
Measured at VDD/2 on the CLKOUT pins  
of the device  
t7  
tJ  
Device-to-Device Skew 2  
Cycle-to-cycle jitter 2  
PLL Lock Time 2  
700  
200  
1.0  
pS  
pS  
Measured at 100MHz, loaded outputs  
Stable power supply, valid clock  
presented on REF pin  
tLOCK  
mS  
Notes:  
1. All parameters specified with loaded outputs.  
2. Parameter is guaranteed by design and characterization. Not 100% tested in production  
Multiple Output Timing-Safe™ Peak EMI reduction IC  
6 of 14  
Notice: The information in this document is subject to change without notice.