PCS5P23Z05D
PCS5P23Z09D
May 2007
rev 0.2
Select Input Decoding for PCS5P23Z09D
PLL
Shut-Down
S2
S1
Clock A1 - A4
Clock B1 - B4
CLKOUT1
Output Source
0
0
1
1
0
1
0
1
Three-state
Driven
Three-state
Three-state
Driven
Driven
Driven
Driven
Driven
PLL
PLL
N
N
Y
N
Driven
Reference
PLL
Driven
Driven
Notes:1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and
the output.
Zero Delay and Skew Control
For applications requiring zero input-output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero-input-output
delay.
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input-output delay.
Multiple Output Timing-Safe™ Peak EMI reduction IC
2 of 14
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
