PCS5P23Z05D
PCS5P23Z09D
May 2007
rev0.2
Input-Output Skew
Test Circuit
Timing-Safe™
Output
Input
TEST CIRCUIT
VDD
+3.3V
CLOAD
0.1uF
TSKEW
+
TSKEW
-
OUTPUT
+3.3V
VDD
GND
0.1uF
One clock cycle
N=1
GND
T
SKEW represents input-output skew
when spread spectrum is ON
For example, TSKEW = ± 0.075 for an
Input clock140MHz, translates in to
(1/140MHz) * 0.075=0.53nS
A Typical example of Timing-Safe™ waveform
Input
Input
CLKOUT with SSOFF
Timing-Safe™ CLKOUT
Multiple Output Timing-Safe™ Peak EMI reduction IC
8 of 14
Notice: The information in this document is subject to change without notice.