PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Pin Configuration for PCS3P624Z09B/C
1
16
DLY_CTRL
CLKOUTA4
CLKIN
2
3
CLKOUTA1
CLKOUTA2
15
14
CLKOUTA3
VDD
13
12
4
5
6
VDD
GND
PCS3P624Z09B/C
GND
CLKOUTB1
11 CLKOUTB4
10
9
CLKOUTB3
S1
7
8
CLKOUTB2
S2
Pin Description for PCS3P624Z09B/C
Pin #
1
Pin Name
CLKIN1
CLKOUTA12
CLKOUTA22
VDD
Pin Type
Description
I
External reference Clock input, 5V tolerant input
Buffered clock Bank A output4
Buffered clock Bank A output4
3.3V supply
2
O
O
P
P
O
O
I
3
4
5
GND
Ground
6
CLKOUTB12
CLKOUTB22
S23
Buffered clock Bank B output4
Buffered clock Bank B output4
7
8
Select input, bit 2.See Select Input Decoding table for PCS3P624Z09 for more details
9
S13
I
Select input, bit 1.See Select Input Decoding table for PCS3P624Z09 for more details
10
11
12
13
14
15
16
CLKOUTB32
CLKOUTB42
GND
O
O
P
P
O
O
O
Buffered clock Bank B output4
Buffered clock Bank B output4
Ground
VDD
3.3V supply
Buffered clock Bank A output4
Buffered clock Bank A output4
CLKOUTA32
CLKOUTA42
DLY_CTRL2
External Input-Output Delay control. This pin can be used as clock output
Notes: 1. Weak pull down
2. Weak pull-down on all outputs
3. Weak pull-up on these Inputs
4. Buffered clock output is Timing-Safe™
High Frequency Timing-Safe™ Peak EMI Reduction IC
4 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
