PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
High Frequency Timing-Safe™ Peak EMI reduction IC
with Peak EMI reduction. PCS3P624Z05 is an eight-pin
version, accepts one reference input and drives out five
low-skew Timing-Safe™ clocks. PCS3P624Z09 accepts
one reference input and drives out nine low-skew Timing-
Safe™clocks.
General Features
•
High Frequency Clock distribution with Timing-
Safe™ Peak EMI Reduction
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•
Input frequency range: 50MHz - 100MHz
Multiple low skew Timing-safe™ Outputs:
PCS3P624Z05: 5 Outputs
PCS3P624Z05/09 has a DLY_CTRL for adjusting the
Input-Output clock delay, depending upon the value of
capacitor connected at this pin to GND.
PCS3P624Z09: 9 Outputs
•
•
•
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External Input-Output Delay Control option
Supply Voltage: 3.3V±0.3V
PCS3P624Z05/09 operates from a 3.3V supply and is
available in two different packages, as shown in the
ordering information table, over commercial and Industrial
temperature range.
Commercial and Industrial temperature range
Packaging Information:
ASM3P624Z05: 8 pin SOIC, and TSSOP
ASM3P624Z09:16 pin SOIC, and TSSOP
True Drop-in Solution for Zero Delay Buffer,
ASM5P2305A / 09A
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Application
PCS3P624Z05/09 is targeted for use in Displays and
memory interface systems.
Functional Description
PCS3P624Z05/09 is a versatile, 3.3V Zero-delay buffer
designed to distribute high frequency Timing-Safe™ clocks
General Block Diagram
DLY_CTRL
DLY_CTRL
PLL
PLL
MUX
CLKIN
CLKOUTA1
CLKOUTA2
CLKOUTA3
CLKOUT1
CLKOUT2
CLKOUT3
CLKIN
CLKOUTA4
CLKOUTB1
PCS3P624Z05B/C
CLKOUT4
S2
S1
Select Input
Decoding
CLKOUTB2
CLKOUTB3
CLKOUTB4
PCS3P624Z09B/C
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
