PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Device - Device Skew
VDD/2
CLKOUT, Device 1
CLKOUT, Device 2
VDD/2
t 7
Test Circuit
Input-Output Skew
Timing-Safe™
Output
+3.3V
Input
VDD
0.1uF
CLKOUT
LOAD
OUTPUT
TSKEW
+
TSKEW
-
+3.3V
VDD
GND
One clock cycle
N=1
0.1uF
T
SKEW represents input-output skew
when spread spectrum is ON
For example, TSKEW = ± 0.125 for an
Input clock12MHz, translates in to
(1/12MHz) * 0.125=10.41nS
A Typical example of Timing-Safe™ waveform
Input
Input
Timing-Safe™ CLKOUT
CLKOUT with SSOFF
High Frequency Timing-Safe™ Peak EMI Reduction IC
8 of 15
Notice: The information in this document is subject to change without notice.