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PCS2P5T915AG 参数 Datasheet PDF下载

PCS2P5T915AG图片预览
型号: PCS2P5T915AG
PDF下载: 下载PDF文件 查看货源
内容描述: 低电压( 2.5V )高精度1 : 5时钟扇出缓冲器 [Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer]
分类和应用: 时钟
文件页数/大小: 23 页 / 793 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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September 2006  
PCS2P5T915A  
rev 0.2  
AC Electrical Characteristics Over Operating Range5  
Symbo  
Parameter  
Min  
Typ  
Max  
Unit  
l
Skew Parameters  
Single-Ended and Differential  
25  
Same Device Output  
Pin-to-Pin Skew1  
Modes  
tSK(O)  
tSK(INV)  
tSK(P)  
pS  
pS  
pS  
Single-Ended in Differential  
Mode (DSE)  
25  
Single-Ended and Differential  
Modes  
300  
300  
Inverting Skew2  
Pulse Skew3  
Single-Ended in Differential  
Mode (DSE)  
300  
300  
Single-Ended and Differential  
Modes  
Single-Ended in Differential  
Mode (DSE)  
Single-Ended and Differential  
Modes  
300  
tSK(PP)  
Part-to-Part Skew4  
pS  
Single-Ended in Differential  
Mode (DSE)  
300  
HSTL and eHSTL Differential True and Complementary  
VOX  
VDDQ/2 - 200  
VDDQ/2  
VDDQ/2 + 200  
mV  
Output Crossing Voltage Level  
Propagation Delay  
Propagation Delay A to  
2.5V / 1.8V LVTTL Outputs  
2.5  
2
tPLH  
tPHL  
nS  
pS  
Qn/Qn  
HSTL / eHSTL Outputs  
2.5V /1.8V LVTTL Outputs  
HSTL / eHSTL Outputs  
2.5V /1.8V LVTTL Outputs  
HSTL / eHSTL Outputs  
Output Rise Time  
(20% to 80%)  
350  
350  
350  
350  
1050  
1350  
1050  
1350  
250  
200  
tR  
tF  
fO  
Output Fall Time  
(20% to 80%)  
pS  
Frequency Range (HSTL/eHSTL outputs)  
Frequency Range (2.5V/1.8V LVTTL outputs)  
MHz  
Output Gate Enable/Disable Delay  
Output Gate Enable to Qn/Qn  
tPGE  
3.5  
3
nS  
nS  
Output Gate Enable to Qn/Qn Driven to GL Designated  
Level  
tPGD  
Notes: 1. Skew measured between all outputs or output pairs under identical input and output interfaces, transitions and load conditions on any one device. For  
single ended and differential LVTTL outputs, this measurement is made when each output voltage passes through VDDQ/2. For differential LVTTL  
outputs, the true outputs are compared only with other true outputs and the complementary outputs are compared only with other complementary  
outputs. For differential HSTL outputs, the measurement takes place at the crossing point of the true and complementary signals.  
2. For operating with either 1.8V or 2.5V LVTTL output interfaces with both true and complementary outputs enabled. Inverting skew is the skew between  
true and complementary outputs switching in opposite directions under identical input and output interfaces, transitions and load conditions on any one  
device.  
3. Skew measured is the difference between propagation delay times tPHL and tPLH of any output or output pair under identical input and output interfaces,  
transitions and load conditions on any one device. For single ended and differential LVTTL outputs, this measurement is made when each output  
voltage passes through VDDQ/2. The measurement applies to both true and complementary signals. For differential HSTL outputs, the measurement  
takes place at the crossing point of the true and complementary signals.  
4. Skew measured is the magnitude of the difference in propagation times between any outputs or output pairs of two devices, given identical transitions  
and load conditions at identical VDD/VDDQ levels and temperature.  
5. Guaranteed by design.  
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer  
13 of 23  
Notice: The information in this document is subject to change without notice.