November 2006
ASM5P23S04A
rev 1.4
Switching Characteristics for ASM5P23S04A Commercial Temperature Devices
Parameter
Description
Test Conditions
Min Typ Max Unit
1/t1
1/t1
1/t1
Output Frequency
30 pF load, All devices
20 pF load, -1H, -2H devices
15 pF load, -1, -2 devices
15
15
15
100 MHz
133 MHz
133 MHz
Output Frequency
Output Frequency
Duty Cycle 5= (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = 66.66 MHz
40.0 50.0 60.0
%
%
30 pF load
Duty Cycle 5 = (t2 / t1) * 100
(-1, -2,-1H, -2H)
Measured at 1.4V, FOUT = <50 MHz
15 pF load
45.0 50.0 55.0
Output Rise Time 5
(-1, -2)
Measured between 0.8V and 2.0V
t3
t3
t3
t4
t4
t4
2.20
1.50
1.50
2.20
1.50
1.25
nS
nS
nS
nS
nS
nS
30 pF load
Output Rise Time 5
(-1, -2)
Measured between 0.8V and 2.0V
15 pF load
Output Rise Time 5
(-1H, -2H)
Measured between 0.8V and 2.0V
30 pF load
Output Fall Time 5
(-1, -2)
Measured between 2.0V and 0.8V
30 pF load
Output Fall Time 5
(-1, -2)
Measured between 2.0V and 0.8V
15 pF load
Output Fall Time 5
(-1H, -2H)
Measured between 2.0V and 0.8V
30 pF load
Output-to-output skew on same bank
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
200
200
200
(-1, -2) 5
Output-to-output skew (-1H, -2H)
t5
pS
Output bank A -to- output bank B skew
(-1, -2H)
Output bank A to output bank B skew (-
2)
All outputs equally loaded
Measured at VDD /2
400
Delay, REF Rising Edge to FBK Rising
t6
t7
0
0
±250 pS
Edge 5
Measured at VDD/2 on the FBK pins of
the device
Device-to-Device Skew 5
Output Slew Rate5
500
pS
Measured between 0.8V and 2.0V
t8
using
1
V/nS
Test Circuit #2
Measured at 66.67 MHz, loaded
175
200
100
400
375
1.0
outputs, 15 pF load
Cycle-to-cycle jitter 5
(-1, -1H, -2H)
Measured at 66.67 MHz, loaded
outputs, 30 pF load
tJ
pS
Measured at 133 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded
outputs, 30 pF load
Cycle-to-cycle jitter 5
(-2)
tJ
pS
Measured at 66.67 MHz, loaded
outputs, 15 pF load
Stable power supply, valid clock
presented on REF and FBK pins
tLOCK
PLL Lock Time 5
mS
Note:
5. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3 ‘SpreadTrak’ Zero Delay Buffer
6 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
