November 2006
rev 1.4
ASM5P23S04A
Switching Characteristics for ASM5I23S04A Industrial Temperature Devices
Parameter
Description
Test Conditions
Min Typ Max Unit
t1
t1
t1
Output Frequency
30 pF load, All devices
15
15
15
100
133
133
MHz
MHz
MHz
Output Frequency
Output Frequency
20 pF load, -1H, -2H devices
15 pF load, -1 and -2 devices
Duty Cycle 8 = (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <66.66 MHz
40.0 50.0 60.0
%
30 pF load
Duty Cycle 8= (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <50 MHz
15 pF load
45.0 50.0 55.0
%
Output Rise Time 8
(-1, -2)
Measured between 0.8V and 2.0V
t3
t3
t3
t4
t4
t4
2.50
1.50
1.50
2.50
1.50
1.25
nS
nS
nS
nS
nS
nS
30 pF load
Output Rise Time 8
(-1, -2)
Measured between 0.8V and 2.0V
15 pF load
Output Rise Time 8
(-1H, -2H)
Measured between 0.8V and 2.0V
30 pF load
Output Fall Time 8
(-1, -2)
Measured between 2.0V and 0.8V
30 pF load
Output Fall Time 8
(-1, -2)
Measured between 2.0V and 0.8V
15 pF load
Output Fall Time 8
(-1H, -2H)
Measured between 2.0V and 0.8V
30 pF load
Output-to-output skew on same bank (-
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
200
200
200
1, -2) 8
Output-to-output skew (-1H, -2H)
t5
pS
Output bank A -to- output bank B skew
(-1, -2H)
Output bank A -to- output bank B skew
(-2)
All outputs equally loaded
Measured at VDD /2
400
Delay, REF Rising Edge to FBK Rising
t6
t7
t8
0
0
±250
500
pS
pS
Edge 8
Measured at VDD/2 on the FBK pins of
the device
Device-to-Device Skew 8
Output Slew Rate8
Measured between 0.8V and 2.0V
1
V/nS
using Test Circuit #2
Measured at 66.67 MHz, loaded
outputs,15 pF load
180
200
Cycle-to-cycle jitter 8
(-1, -1H, -2H)
Measured at 66.67 MHz, loaded
tJ
pS
outputs,
30 pF load
Measured at 133 MHz, loaded
100
400
380
1.0
outputs, 15 pF load
Measured at 66.67 MHz, loaded
outputs, 30 pF load
Cycle-to-cycle jitter 8
(-2)
tJ
pS
Measured at 66.67 MHz, loaded
outputs, 15 pF load
Stable power supply, valid clock
presented on REF and FBK pins
tLOCK
PLL Lock Time 8
mS
Note:
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3 ‘SpreadTrak’ Zero Delay Buffer
8 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
