November 2006
rev 1.4
ASM5P23S04A
Pin Configuration
FBK
VDD
1
REF
CLKA1
CLKA2
GND
8
2
3
4
7
6
ASM5P23S04A
CLKB2
CLKB1
5
Pin Description for ASM5P23S04A
Pin #
Pin Name
Description
1
2
3
4
5
6
7
8
REF1
CLKA12
CLKA22
GND
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
Ground
CLKB12
CLKB2 2
VDD
Buffered clock output, bank B
Buffered clock output, bank B
3.3V supply
FBK
PLL feedback input
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3.3 ‘SpreadTrak’ Zero Delay Buffer
3 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
