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ASM3P623S00AF-08-TT 参数 Datasheet PDF下载

ASM3P623S00AF-08-TT图片预览
型号: ASM3P623S00AF-08-TT
PDF下载: 下载PDF文件 查看货源
内容描述: [PLL Based Clock Driver, 3P Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 4.40 MM, ROHS COMPLIANT, TSSOP-8]
分类和应用: 光电二极管
文件页数/大小: 16 页 / 297 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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July 2005  
ASM3P623S00A/B/C/D/E/F  
rev 1.0  
Differential cycle slip  
Modulated  
Output  
Input  
-Nd  
+Nd  
One clock cycle  
N=1  
Nd represents the differential cycle slip  
when spread spectrum is ON  
Nd = ± 0.125 in the example  
Test Circuits  
TEST CIRCUIT # 1  
VDD  
CLKOUT  
OUTPUTS  
0.1uF  
0.1uF  
CLOAD  
VDD  
GND  
GND  
Zero Cycle Slip Peak EMI Reduction IC  
7 of 16  
Notice: The information in this document is subject to change without notice.  
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