May 2008
rev 0.5
ASM3P622S00B/E
Input-Output Skew
Test Circuit
Timing-Safe™
Output
Input
+3.3V
VDD
TSKEW
+
0.1uF
0.1uF
TSKEW
-
CLKOUT
LOAD
OUTPUT
+3.3V
Test Circuit
VDD
One clock cycle
N=1
GND
T
SKEW represents input-output skew
when spread spectrum is ON
For example, TSKEW = ± 0.125 for an
Input clock12MHz, translates in to
(1/12MHz) * 0.125=10.41nS
A Typical example of Timing-Safe™ waveform
Input
Input
CLKOUT with SSOFF
Timing-Safe™ CLKOUT
Low Frequency Timing-Safe™ Peak EMI Reduction IC
8 of 15
Notice: The information in this document is subject to change without notice.