May 2008
rev 0.5
ASM3P622S00B/E
Switching Characteristics for ASM3P622S00B/E
Parameter
Test Conditions
Min
4
Typ
Max
20
Unit
MHz
MHz
%
Input Frequency
Output Frequency
30pF load
4
20
Duty Cycle 6,7 = (t2 / t1) * 100
Output Rise Time 7, 8
Output Fall Time 7, 8
Output-to-output skew 7, 8
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge 8
Measured at VDD/2
40
50
60
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded with SSOFF
2.5
2.5
250
nS
nS
pS
Measured at VDD /2 with SSOFF
±350
700
pS
pS
Measured at VDD/2 on the CLKOUT pins
of the device
Device-to-Device Skew 8
Cycle-to-Cycle Jitter 7, 8
PLL Lock Time 8
< 8MHz
Loaded outputs
±1.6
nS
pS
> 8MHz
±200
Stable power supply, valid clock presented
on CLKIN pin
1.0
mS
Note: 7. All parameters specified with 30pF loaded outputs.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production
Switching Waveforms
Duty Cycle Timing
t1
t2
VDD/2
VDD/2
VDD/2
OUTPUT
All Outputs Rise/Fall Time
2V
2V
0.8V
3.3V
0.8V
OUTPUT
0V
t3
t4
Low Frequency Timing-Safe™ Peak EMI Reduction IC
6 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
