TISPPBL1D, TISPPBL1P, TISPPBL2D, TISPPBL2P
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
FOR ERICSSON COMPONENTS SLICS
AUGUST 1997 - REVISED DECEMBER 1999
The negative protection voltage will be the sum of the gate supply (V
B
) and the peak gate(terminal)-cathode
voltage (V
GK(BO)
). Under a.c. overvoltage conditions V
GK(BO)
will be less than 3 V. The integrated transistor
buffer in the TISPPBLx greatly reduces the gate positive current (from about 50 mA to 1 mA) and introduces a
negative gate current. Figure 1 shows that the TISPPBLx gate current depends on the current being
conducted by the principal terminals. The gate current is positive during clipping (charging the V
B
supply) and
negative when the thyristor is on or the diode is conducting (loading the V
B
supply). Without the negative gate
current and the reduced level of positive gate current the V
B
supply could be charged with a current of nearly
100 mA. As the V
B
supply is likely to be electronic it would not be designed to be charged like a battery. As a
result, the SLIC could be destroyed by the voltage of V
B
increasing to a level that exceeded the SLIC’s
capability on the V
BAT
pin. The integrated transistor buffer removes this problem.
Fast rising impulses will cause short term overshoots in gate-cathode voltage. The negative protection
voltage under impulse conditions will also be increased if there is a long connection between the gate
decoupling capacitor, C1, and the gate terminal. During the initial rise of a fast impulse, the gate current (I
G
) is
the same as the cathode current (I
K
). Rates of 60 A/µs can cause inductive voltages of 0.6 V in 2.5 cm of
printed wiring track. To minimise this inductive voltage increase of protection voltage, the length of the
capacitor to gate terminal tracking should be minimised. Inductive voltages in the protector cathode wiring
can increase the protection voltage. These voltages can be minimised by routing the SLIC connection through
the protector as shown in Figure 13 and Figure 14.
SLIC
PROTECTION
TISPPBLx
Th4
SLIC
PROTECTION
TISPPBLx
Th4
SLIC
I
T
Th5
I
F
Th5
SLIC
V
B
AI6XANB
V
Bat
C1
D1
C2
AI6XAOB
V
B
V
Bat
C1
D1
C2
Figure 13 NEGATIVE OVERVOLTAGE CONDITION
Figure 14 POSITIVE OVERVOLTAGE CONDITION
Positive overvoltages (Figure 14) are clipped to ground by forward conduction of the diode section in the
TISPPBLx. Fast rising impulses will cause short term overshoots in forward voltage (V
FRM
).
TISPPBLx limiting voltages
This clause details the TISPPBLx voltage limiting levels under impulse conditions.
test circuit
impulse, the high levels of electrical energy and rapid rates of change cause electrical noise to be induced or
conducted into the measurement system. It is possible for the electrical noise voltage to be many times the
wanted signal voltage. Elaborate wiring and measurement techniques where used to reduce the noise
voltage to less than 2 V peak to peak.
PRODUCT
INFORMATION
9
POINN [ POWER INNOVATIONS LTD ]
