Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 8. LCS Cell Sliced Across Dataslices and Crossbars
ETT1 Port
ETT1 Port
LCS Cell
Crossbar 0
Dataslice
Dataslice
Slices 0,1
LCS Header
(8 Bytes)
Slices 0,1
Crossbar 1
Crossbar 2
Dataslice
Dataslice
Slices 2,3
Slices 2,3
Crossbar 3
Payload
(64 Bytes)
Crossbar 10
Dataslice
Dataslice
Slices 10,11
Crossbar 11
Slices 10,11
Crossbar 12
Dataslice
Dataslice
Extra 12 bytes
(6 bytes per slice)
Slices 12,13
Crossbar 13
Slices 12,13
The 64 byte payload cell requires six Dataslices per port and 12 Crossbars (32 port, non-redundant). The
76 byte payload cell requires seven Dataslices per port and 14 Crossbars. The EPP is capable of
supporting the seventh Dataslice.
Because the extra data is obtained by slicing the cell then this does not affect the clock frequency of the
Chip Set. The only effect is that the link between the ETT1 port and the linecard must go up from 18 Gbaud
to 21 Gbaud. This is done by making the link wider, not faster.
1.2.9.2 8, 16, or 32 ports
The ETT1 core can support a maximum of 32 ports. Smaller configurations can be supported by simply not
using some of the ports. However, if the maximum system is an eight or 16 port configuration, then some
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
29
PMC [ PMC-SIERRA, INC ]
