Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
to provide TDM synchronization event information, and can recover from any grant/credit information that
is lost if cells are corrupted in transmission.
1.2.7.1 Sending a Control Packet from the OOB to the Linecard
Before sending a CPU (OOB to linecard) control packet, the OOB must first write the control packet header
and payload data into the appropriate locations in the Dataslice. (See Section 3.3 “Output Dataslice Queue
Memory Allocation with EPP”, Table 23, on page 164.) The header for customer-specific CPU control
packets should be written into the Dataslices as shown, but the payload data is completely up to the
customer.
To send the CPU control packet which has been written into Dataslice queue memory, the OOB writes the
ESOBLCP register with the control packet type select in bits [5:4] (see the bit-breakout), and a linecard
fanout in bits [3:0]. If the port is connected to 4 subport linecards, then bits [3:0] are a subport-bitmap. If
the port is connected to one OC-192c linecard, then bit 0 must be set when the OOB wishes to send a CP.
When the CP has been sent to the linecard(s) indicated in bits [3:0], bits [3:0] will read back as 0. Since
control packets have higher priority than any other traffic type, they will be sent immediately, unless the
EPP is programmed to send only idle cells.
1.2.7.2 Sending a Control Packet From the Linecard to the OOB
The linecard sends control packets to OOB using the regular LCS request/grant/cell mechanism. A CPU
(linecard to OOB) control packet must have the CPU bit set in its request label (See Section 1.1.3 “The
LCS Protocol” on page 17.) When the EPP receives the cell payload for a CPU control packet, it stores the
cell in the Dataslices’ Input Queue memories and raises the “Received LC2OOB/CPU Control Packet from
Linecard...” interrupt. (In OC-192c mode, it will always be Linecard 0.)
The input queue for CPU control packets from each linecard is only 8 cells deep, so as soon as the OOB
sees a “Received LC2OOB...” interrupt, it should read the appropriate “Subport* to OOB FIFO Status”
register (0x80..0x8c). Bit [3:0] of that register will tell how many control packet cells are currently in the
input queue; bits 6:4 will tell the offset of the head the 8-cell CPU CP input queue. That queue offset
should be used to form addresses for the Dataslices’ Input Queue memories. See Section 3.2 “Input
Dataslice Queue Memory Allocation with EPP” on page 162, for Dataslice Input Queue memory
addressing. Then the OOB should read those addresses to obtain the CPU CP payload data. When the
OOB has read the CPU CP payload data, it should write the appropriate “Linecard * to OOB FIFO Status”
register (any value). A write to that register, regardless of the write data, will cause the head of the queue
to be dequeued, freeing up that space in the CPU CP input queue.
See Section 1.6.3 “Control Packets” on page 69 for more details.
1.2.8 Redundancy
An ETT1 core can be configured with certain redundant (duplicated) elements. A fully redundant core is
capable of sustaining single errors within any shared device without losing or re-ordering any cells. This
section describes the main aspects of a redundant core. A complete switch may have two ETT1 cores,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
