Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
with linecards dual-homed to both cores, and while this is a valid configuration the ETT1 core does not
provide any specific support for such a configuration.
Figure 6 shows a fully redundant core. The Crossbars and Scheduler are fully replicated, as are the links
connecting those devices. The port devices (EPP and Dataslices) are not replicated. It is important to
understand that if an EPP or Dataslice fails (or incurs a transient internal error), then data may be lost, but
only within that port.
Figure 6. Fully Redundant Core
Crossbar 0
Dataslice
Dataslice
Crossbar 1
EPP
EPP
Flow Control
Crossbar 0
Port
Port
Flow Control
Crossbar 1
Scheduler 0
Scheduler- 1
Fault tolerant region
A fully redundant core operates in exactly the same way as a non-redundant core. Consider the EPP: it
sends new request information to both Schedulers. The two Schedulers operate synchronously, producing
identical outputs, and the information (grants) received by the EPP will be the same. The Dataslices
operate in exactly the same way with their two Crossbar devices.
26
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
