PRELIMINARY
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Table 25. Enhanced Port Processor Signal Descriptions (Continued)
Name
oob_devsel3
I/O
Type
Description
OOB Device Select
I
CMOS
EPP/DS Interface
HSTL
Class 1
DS to EPP ingress data unmodified
DS to EPP egress data
d2p_d0_id[7:0]
d2p_d0_od[7:0]
d2p_d1_id[7:0]
d2p_d1_od[7:0]
d2p_d2_id[7:0]
p2d_d[6:0]_ic[7:0]
p2d_d[6:0]_oc[7:0]
p2d_d0_id[7:0]
I
I
HSTL
Class 1
HSTL
Class 1
DS to EPP ingress data unmodified
DS to EPP egress data
I
HSTL
Class 1
I
HSTL
Class 1
DS to EPP ingress data unmodified
EPP to DS ingress control
I
HSTL
Class 1
O
O
O
HSTL
Class 1
EPP to DS egress control
HSTL
Class 1
EPP to DS ingress data modified
EPP to DS ingress data modified
Input Reference Voltage
HSTL
Class 1
p2d_d1_id[7:0]
Vref
O
I
HSTL
AIB Interface
EPP to Sched AIB
p2s_s0_[c cn, e, en, o,
on]
O
O
I
STI
STI
STI
STI
STI
p2s_s1_[c cn, e, en, o,
on]
EPP to Sched AIB
Sched to EPP AIB
Sched to EPP AIB
Fc Crossbar to EPP AIB
s2p_s0_[c cn, e, en, o,
on]
s2p_s1_[c cn, e, en, o,
on]
I
f2p_a0_[c cn, e, en, o,
on]
I
210
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE