PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
RPFEE:
The receive packet format error interrupt enable bit (RPFEE) enables receive
packet format error interrupts to the microprocessor. When RPFEE is set
high, receipt of a packet that is longer than the maximum specified in the
RHDL Maximum Packet Length register, or a packet that is shorter than 32
bits (CRC-CCITT) or 48 bits (CRC-32), or a packet that is not octet aligned
will cause an interrupt to be generated on the INTB output. Interrupts are
masked when RPFEE is set low. However, the RPFEI bit remains valid when
interrupts are disabled and may be polled to detect receive packet format
error events.
RFOVRE:
The receive FIFO overrun error interrupt enable bit (RFOVRE) enables
receive FIFO overrun error interrupts to the microprocessor. When RFOVRE
is set high, attempts to write data into the logical FIFO of a channel when it is
already full will cause an interrupt to be generated on the INTB output.
Interrupts are masked when RFOVRE is set low. However, the RFOVRI bit
remains valid when interrupts are disabled and may be polled to detect
receive FIFO overrun events.
TPRTYE:
The transmit parity error interrupt enable bit (TPRTYE) enables parity errors
on the transmit APPI to generate interrupts to the microprocessor. When
TPRTYE is set high, detection of a parity error on the transmit APPI will cause
an interrupt to be generated on the INTB output. Interrupts are masked when
TPRTYE is set low. However, the TPRTYI bit remains valid when interrupts
are disabled and may be polled to detect parity error events.
TUNPVE:
The transmit unprovisioned error interrupt enable bit (TUNPVE) enables
attempted transmissions to unprovisioned channels to generate interrupts to
the microprocessor. When TUNPVE is set high, attempts to write data to an
unprovisioned channel will cause an interrupt to be generated on the INTB
output. Interrupts are masked when TUNPVE is set low. However, the
TUNPVI bit remains valid when interrupts are disabled and may be polled to
detect attempted transmissions to unprovisioned channel events.
TFOVRE:
The transmit FIFO overflow error interrupt enable bit (TFOVRE) enables
transmit FIFO overflow error interrupts to the microprocessor. When
TFOVRE is set high, attempts to write data to the logical FIFO when it is
already full will cause an interrupt to be generated on the INTB output.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
68
PMC [ PMC-SIERRA, INC ]
