PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Register 0x000 : FREEDM-84A672 Master Reset
Bit
Type
Function
Default
Bit 15
R/W
Reset
0
Bit 14
to
Unused
XH
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
R
R
R
R
TYPE[3]
TYPE[2]
TYPE[1]
TYPE[0]
ID[7]
ID[7]
ID[5]
ID[4]
ID[3]
0
1
0
1
0
0
0
0
0
0
1
0
ID[2]
ID[1]
ID[0]
This register provides software reset capability and device ID information.
RESET:
The RESET bit allows the FREEDM-84A672 to be reset under software
control. If the RESET bit is a logic one, the entire FREEDM-84A672, except
the microprocessor interface, is held in reset. In addition, all registers are
reset to their default values. This bit is not self-clearing. Therefore, a logic
zero must be written to bring the FREEDM-84A672 out of reset. Holding the
FREEDM-84A672 in a reset state places it into a low power, stand-by mode.
A hardware reset clears the RESET bit, thus negating the software reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
65
PMC [ PMC-SIERRA, INC ]
