PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
9
NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the
FREEDM-84A672.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure software
compatibility with future, feature-enhanced versions of the product, unused register
bits must be written with logic zero. Reading back unused bits can produce either a
logic one or a logic zero; hence, unused register bits should be masked off by
software when read.
2. Except where noted, all configuration bits that can be written into can also be read
back. This allows the processor controlling the FREEDM-84A672 to determine the
programming state of the block.
3. Writable normal mode register bits are cleared to logic zero upon reset unless
otherwise noted.
4. Writing into read-only normal mode register bit locations does not affect FREEDM-
84A672 operation unless otherwise noted.
5. Certain register bits are reserved. These bits are associated with megacell functions
that are unused in this application. To ensure that the FREEDM-84A672 operates
as intended, reserved register bits must only be written with their default values.
Similarly, writing to reserved registers should be avoided.
9.1 Microprocessor Accessible Registers
Microprocessor accessible registers can be accessed by the external
microprocessor. For each register description below, the hexadecimal register
number indicates the address in the FREEDM-84A672 when accesses are made
using the external microprocessor.
Note
These registers are not byte addressable. Writing to any one of these registers
modifies all 16 bits in the register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
64
PMC [ PMC-SIERRA, INC ]
