PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
request from the link with the highest priority for service. When there are no
pending requests, the priority encoder generates an idle cycle. In addition, once
every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no
requests are serviced. This cycle is used by the channel assigner upstream for
CBI accesses to the channel provision RAM.
8.9.3 Channel Assigner
The channel assigner block determines the channel number of the request
currently being processed. The block contains a 2688 word channel provision
RAM. The address of the RAM is constructed from concatenating the link
number and the time-slot number of the highest priority requester. The fields of
each RAM word include the channel number and a time-slot enable flag. The
time-slot enable flag labels the current time-slot as belonging to the channel
indicted by the channel number field. For time-slots that are enabled, the
channel assigner issues a request to the THDL672 block which responds with
packet data within one byte period of the transmit stream.
8.10 SBI Inserter and SIPO
The SBI transmit circuitry consists of an SBI Insert block and three SBI Serial to
Parallel Converter (SBI SIPO) blocks. Each SIPO block processes data for one
of the three Synchronous Payload Envelopes (SPEs) conveyed on the SBI ADD
BUS. It receives serial data on either 28 links running at T1/J1 rate, 21 links at
E1 rate or a single link at DS-3 rate and converts it to an internal parallel bus
format. The SBI Insert block receives data from the SIPO blocks in the internal
format and transmits it on the SBI ADD BUS.
The SIPO blocks generate the serial clocks for the TCAS672 and thus are able to
control the rate at which data is transmitted on to the SBI. The SBI Insert block
can command the SIPO blocks to speed up or slow down these clocks in
response to justfication requests received on the SBI interface. The SBI Insert
block also contains FIFO circuitry to compensate for short term variations in the
rate at which data is output by the TCAS672 and the rate at which it is
transmitted on the SBI ADD BUS.
The SBI Insert block may be configured to enable or disable transmission of
individual tributaries on to the SBI ADD bus. Individual tributaries may also be
configured to operate in framed or unframed mode.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
