PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
8.11 Performance Monitor
The Performance Monitor block (PMON) contains four counters. The first two
accumulate receive partial packet buffer FIFO overrun events and transmit partial
packet buffer FIFO underflow events, respectively. The remaining two counters
are software programmable to accumulate a variety of events, such as receive
packet count, FCS error counts, etc. All counters saturate upon reaching
maximum value. The accumulation logic consists of a counter and holding
register pair. The counter is incremented when the associated event is detected.
Writing to the FREEDM-84A672 Master Clock / Frame Pulse Activity Monitor and
Accumulation Trigger register transfer the count to the corresponding holding
register and clear the counter. The contents of the holding register is accessible
via the microprocessor interface.
8.12 JTAG Test Access Port Interface
The JTAG Test Access Port block provides JTAG support for boundary scan. The
standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions
are supported. The FREEDM-84A672 identification code is 073850CD
hexadecimal.
8.13 Microprocessor Interface
The FREEDM-84A672 supports microprocessor access to an internal register
space for configuring and monitoring the device. All registers are 16 bits wide but
are DWORD aligned in the microprocessor memory map. The registers are
described below:
Table 11 – Normal Mode Microprocessor Accessible Registers
Address
Register
0x000
0x004
0x008
0x00C
FREEDM-84A672 Master Reset
FREEDM-84A672 Master Interrupt Enable
FREEDM-84A672 Master Interrupt Status
FREEDM-84A672 Master Clock / Frame Pulse Activity
Monitor and Accumulation Trigger
0x010
FREEDM-84A672 Reserved
0x014
0x018 – 0x020
FREEDM-84A672 Master Line Loopback
FREEDM-84A672 Reserved
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
59
PMC [ PMC-SIERRA, INC ]
