PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
8
FUNCTIONAL DESCRIPTION
8.1 Scaleable Bandwidth Interconnect (SBI) Interface
The Scaleable Bandwidth Interconnect is a synchronous, time-division
multiplexed bus designed to transfer, in a pin-efficient manner, data belonging to
a number of independently timed links of varying bandwidth. The bus is timed to
a reference 19.44MHz clock and a 2 kHz or 166.7Hz frame pulse. All sources
and sinks of data on the bus are timed to the reference clock and frame pulse.
Timing is communicated across the Scaleable Bandwidth Interconnect by floating
data structures. Payload indicator signals in the SBI control the position of the
floating data structure and therefore the timing. When sources are running faster
than the SBI the floating payload structure is advanced by an octet by passing an
extra octet in the V3 octet locations (H3 octet for DS3 mappings). When the
source is slower than the SBI the floating payload is retarded by leaving the octet
after the V3 or H3 octet unused. Both these rate adjustments are indicated by
the SBI control signals.
An SBI interface consists of a DROP BUS and an ADD BUS. On the DROP BUS
all timing is sourced from the PHY and is passed onto the FREEDM-84A672 by
the arrival rate of data over the SBI. On the ADD BUS timing can be controlled
by either the PHY or the FREEDM-84A672. When the FREEDM-84A672 is the
timing master, the PHY device determines its transmit timing information from the
arrival rate of data across the SBI. When the PHY device is the timing master, it
signals the FREEDM-84A672 to speed up or slow down with justification request
signals. The PHY timing master indicates a speedup request to the Link Layer
by asserting the justification request signal high during the V3 or H3 octet. When
this is detected by the FREEDM-84A672 it will advance the channel by inserting
data in the next V3 or H3 octet as described above. The PHY timing master
indicates a slowdown request to the FREEDM-84A672 by asserting the
justification request signal high during the octet after the V3 or H3 octet. The
FREEDM-84A672 responds by leaving the octet following the next V3 or H3 octet
unused. Both advance and retard rate adjustments take place in the frame or
multi-frame following the justification request.
The SBI multiplexing structure is modeled on the SONET/SDH standards. The
SONET/SDH virtual tributary structure is used to carry T1/J1 and E1 links.
Unchannelized DS3 payloads follow a byte synchronous structure modeled on
the SONET/SDH format.
The SBI structure uses a locked SONET/SDH structure fixing the position of the
TUG-3/TU-3 relative to the STS-3/STM-1 transport frame. The SBI is also of fixed
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
39
PMC [ PMC-SIERRA, INC ]
