PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
10
TEST FEATURES DESCRIPTION
The FREEDM-84A672 also supports a standard IEEE 1149.1 five signal JTAG
boundary scan test port for use in board testing. All device inputs may be read
and all device outputs may be forced via the JTAG test port.
10.1 Test Mode Registers
Test mode registers are used to apply test vectors during production testing of
the FREEDM-84A672. Production testing is enabled by asserting the PMCTEST
pin. During production tests, FREEDM-84A672 registers are selected by the
TA[12:0] pins. Read accesses are enabled by asserting TRDB low while write
accesses are enabled by asserting TWRB low. Test mode register data is
conveyed on the TDAT[15:0] pins. Test mode registers (as opposed to normal
mode registers) are selected when TA[12]/TRS is set high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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