PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Register 0x690 : SBI INSERT Tributary RAM Indirect Access Control
Bit
Type
Function
Default
Bit 15
to
Unused
XXH
Bit 8
Bit 7
R/W
BUSY
X
Bit 6
to
Unused
XXH
Bit 2
Bit 1
Bit 0
R/W
R/W
RWB
Reserved
0
0
This register controls access to the SBI INSERT tributary control configuration
RAM. Writing to this register triggers an indirect register access.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM-
84A672 device.
RWB
The indirect access control bit (RWB) selects between a configure (write) or
interrogate (read) access to the tributary control configuration RAM. Writing a
‘0’ to RWB triggers an indirect write operation. Data to be written is taken
from the SBI INSERT Tributary RAM Indirect Access Data Register. Writing a
‘1’ to RWB triggers an indirect read operation. The data read can be found in
the SBI INSERT Tributary RAM Indirect Access Data Register.
BUSY
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when a write to the SBI INSERT Tributary RAM
Indirect Access Control Register triggers an indirect access and will stay high
until the access is complete. This register should be polled to determine
when data from an indirect read operation is available in the SBI INSERT
Tributary RAM Indirect Access Data Register or to determine when a new
indirect write operation may commence.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
178
PMC [ PMC-SIERRA, INC ]
