PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
bits must be written with logic zero. Reading back unused bits can produce either a
logic one or a logic zero; hence unused register bits should be masked off by
software when read.
2. Writable test mode register bits are not initialized upon reset unless otherwise noted.
10.2 JTAG Test Port
The FREEDM-84A672 JTAG Test Access Port (TAP) allows access to the TAP
controller and the 4 TAP registers: instruction, bypass, device identification and
boundary scan. Using the TAP, device input logic levels can be read, device
outputs can be forced, the device can be identified and the device scan path can
be bypassed. For more details on the JTAG port, please refer to the Operations
section.
Table 29 – Instruction Register
Length - 3 bits
Instructions Selected Register
Instruction Code IR[2:0]
EXTEST
IDCODE
SAMPLE
BYPASS
BYPASS
STCTEST
BYPASS
BYPASS
Boundary Scan
Identification
Boundary Scan
Bypass
Bypass
Boundary Scan
Bypass
000
001
010
011
100
101
110
111
Bypass
10.2.1 Identification Register
Length - 32 bits
Version number - 2H
Part Number - 7385H
Manufacturer's identification code - 0CDH
Device identification - 273850CDH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
183
PMC [ PMC-SIERRA, INC ]
