PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Register 0x680 : SBI INSERT Control
Bit
Type
Function
Default
Bit 15
to
Unused
XXH
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Reserved
Unused
Unused
Reserved
Reserved
Reserved
Unused
0
X
X
0
0
0
X
1
R/W
R/W
R/W
R/W
SBI_PAR_CTL
This register controls the operation of the SBI INSERT block.
SBI_PAR_CTL
The SBI_PAR_CTL bit is used to configure the Parity mode for generation of
the SBI parity signal, ADP as follows: When SBI_PAR_CTL is ’0’ parity is
even. When SBI_PAR_CTL is ‘1’ parity is odd.
Reserved:
The reserved bits must be set low for correct operation of the FREEDM-
84A672 device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
176
PMC [ PMC-SIERRA, INC ]
