PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Transmit Channel Descriptor Reference Table
The TMAC672 maintains a Transmit Channel Descriptor Reference (TCDR)
table in which is stored certain information relating to DMA activity on each
channel together with TD pointers which are used by the TMAC672 to sort
packet chains supplied by the host into per-channel linked lists (see below). The
caching of DMA-related information reduces the number of host bus accesses
required to process each data packet, while the sorting into per-channel linked
lists eliminates head of line blocking. Each channel is provided with two entries
in the TCDR table, one for high priority packets (Pri 1) and one for low priority
packets (Pri 0). The structure of the TCDR table is shown in Figure 13 below.
Figure 13 – Transmit Channel Descriptor Reference Table
Bit 0
Current TD Pointer [14:0]
Host TD Pointer [14:0]
Bit 33
TCC 0, Pri 0
Abrt IOC
NA
M
CE
A
D
Reserved (12)
Res
Res
Bytes to Tx [15:0]
Res
DMA Current Address[31:0]
PiP
U
V
Res
Last TD Pointer [14:0]
Next TD Pointer [14:0]
Abrt IOC
NA
M
CE
A
D
Current TD Pointer [14:0]
Host TD Pointer [14:0]
Reserved (12)
TCC 1, Pri 0
Res
Res
Res
Bytes to Tx [15:0]
DMA Current Address[31:0]
Last TD Pointer [14:0]
PiP
U
V
Res
Next TD Pointer [14:0]
Abrt IOC
NA
M
CE
A
D
Current TD Pointer [14:0]
Host TD Pointer [14:0]
Reserved (12)
TCC 671, Pri 1
Res
Res
Res
Bytes to Tx [15:0]
DMA Current Address[31:0]
Last TD Pointer [14:0]
PiP
U
V
Res
Next TD Pointer [14:0]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
68
PMC [ PMC-SIERRA, INC ]
