PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Transmit Queues
Pointers to the transmit descriptors (TDs) containing packet(s) ready for
transmission are passed from the host to the TMAC672 using the Transmit
Descriptor Reference Ready (TDRR) queue, which resides in host memory.
Pointers to transmit descriptor structures whose buffers have been read by the
TMAC672 are passed from the TMAC672 to the host using the Transmit
Descriptor Reference Free (TDRF) queue, which also resides in host memory.
The TMAC672 contains a Free Queue cache which can store up to six TDRs. If
caching is enabled, free TDRs are written into the TDRF queue six at a time, to
reduce the number of host memory accesses. The Free Queue cache is flushed
to the TDRF queue if the Interrupt On Completion (IOC) bit is set in the TD,
which sends the corresponding TDR directly to the TDRF queue. The Free
Queue cache is also flushed to the TDRF queue if the FQFLUSH register bit is
set high. The FQFLUSH register bit is self clearing.
The queues, shown in Figure 12 are defined by a common base pointer residing
in the Transmit Queue Base register and eight offset pointers, four per queue.
For each queue, two pointers define the start and the end of the queue, and two
pointers keep track of the current read and write locations within the queue. The
read pointer for each queue points to the offset of the last valid TDR read, and
the write pointer points to the offset where next TDR can be written. The end of
a queue is not a valid location for a TDR to be read or written. A queue is empty
when the read pointer is one less than the write pointer or if the read pointer is
one less than the end pointer and the write pointer equals the start pointer. A
queue is full when the read pointer is equal to the write pointer. Each queue
element is 32 bits in size, but only the least significant 18 bits are valid. The 18
least significant bits consist of a 15-bit TDR and three status bits for the TD
pointed at by this TDR. The status bits are used by the TMAC672 to inform the
host of the success or failure of transmission (see Table 12). When the
TMAC672 writes TDRs to the TDRF queue, it sets bits [23:18] of the queue
element to 0 and leaves bits [31:24] unaltered. Once a TDR is placed on the
TDRF queue, the FREEDM-84P672 will make no further accesses to the TD nor
the associated buffer.
Note that the maximum value to which an end pointer may be set is FFFF hex,
resulting in a maximum offset from the queue base address of (4*(FFFF-1)) =
3FFF8 hex. An end pointer must not be set to 0 hex in an attempt to include
offset 3FFFC hex in a queue.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
65
PMC [ PMC-SIERRA, INC ]
