PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Field
PiP
Description
The Packet Transfer in Progress bit indicates that a
packet is currently being transmitted on this channel at
this priority level.
Last TD Pointer [14:0] Offset to the head of the last host-linked chain of TDs
to be read. (See Figure 14)
V
Indicates if the linked list of packets for this channel
contains more than one host-linked chain (See Figure
14). If the V bit is set to logic 1, the list contains more
than one chain and the next and last TD pointer fields
are valid. If the V bit is set to logic 0, the list is either
empty or contains only one host-linked chain and the
next and last TD pointer fields are invalid.
Next TD Pointer [14:0] Offset to the head of the next host-linked chain of TDs
to be read. (See Figure 14)
Transmit Descriptor Linking
As described above, the TCDR table contains pointers which the TMAC672 uses
to construct linked lists of data packets to be transmitted. After the host places a
new TDR in the TDR Ready queue, the TMAC672 retrieves the TDR and links it
to the TD pointed at by the Last TD Pointer field. The TMAC672 may create up
to 1,344 linked lists, viz. a high-priority list and a low-priority list for each DMA
channel. Whenever a new data packet is requested by the downstream block,
the TMAC672 picks a packet from the high-priority linked list unless it is empty, in
which case, a packet from the low-priority linked list is used.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
70
PMC [ PMC-SIERRA, INC ]
