PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Figure 12 – TDRR and TDRF Queues
Transmit Descriptor Referance Queues
Base Address:
TQB[31:2] = Tx Queue Base register
Index Registers:
Ready:
TDRRQS[15:0]
= TDR Ready Queue Start register
TDRRQW[15:0] = TDR Ready Queue Write register
TDRRQR[15:0]
TDRRQE[15:0]
=
=
TDR Ready Queue Read register
TDR Ready Queue End register
Base Address
TQB[31:2]
Index[15:0]
00
00
+
+ Index Register
Free:
-------------------------
PCI Address
AD[31:0]
TDRFQS[15:0]
=
TDR Free Queue Start register
TDRFQW[15:0] = TDR Free Queue Write register
TDRFQR[15:0]
TDRFQE[15:0]
=
=
TDR Free Queue Read register
TDR Free Queue End register
Tx Descriptor Reference Queue Memory Map
Bit 31
Bit 0
TDRFQS
TDRFQR
Status + TDR
PCI Host Memory
Status + TDR
Status + TDR
Status + TDR
Status + TDR
TDRFQW
TDRFQE
TQB
256KB
TDR Reference Queues
Status + TDR
TDRRQS
TDRRQR
TDR
TDR
TDR
TDR
TDR
TDR
TDRRQW
TDRRQE
Valid TDR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
66
PMC [ PMC-SIERRA, INC ]
