PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
During Clock 2, the initiator ceases to drive the AD[31:0] bus in order that the
target can drive it in the next cycle. The initiator also drives the C/BEB[3:0] lines
with the byte enables for the read data. IRDYB is driven active by the initiator to
indicate it is ready to accept the data transfer. All subsequent cycles on the PCI
bus are called data phases.
During Clock 3, the target claims the transaction by driving DEVSELB active. It
also places the first data word onto the AD[31:0] bus and drives TRDYB to
indicate to the initiator that the data is valid.
During Clock 4, the initiator latches in the first data word. The target negates
TRDYB to indicate to the initiator that it is not ready to transfer another data
word.
During Clock 5, the target places the second data word onto the AD[31:0] bus
and drives TRDYB to indicate to the initiator that the data is valid.
During Clock 6, the initiator latches the second data word and negates IRDYB to
indicate to the target that it is not ready for the next transfer. The target shall
drive the third data word until the initiator accepts it.
During Clock 7, the initiator asserts IRDYB to indicate to the target it is ready for
the third data word. It also negates FRAMEB since this shall be the last transfer.
During Clock 8, the initiator latches in the last word and negates IRDYB. The
target, having seen FRAMEB negated in the last clock cycle, negates TRDYB
and DEVSELB. All of the above signals shall be driven to their inactive state in
this clock cycle, except for FRAMEB which shall be tristated. The target shall
stop driving the AD[31:0] bus and the initiator shall stop driving the C/BEB[3:0]
bus; this shall be the turnaround cycle for these signals.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
324
PMC [ PMC-SIERRA, INC ]
