PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
14
FUNCTIONAL TIMING
14.1 SBI DROP BUS Interface Timing
Figure 22 – T1/E1 DROP BUS Functional Timing
REFCLK
SSS
C1FP
SSS
DDATA[7:0]
DPL
C1
V3
V3
V3 DS0#4. V5 DS0#9.
SSS
SSS
SSS
SSS
DV5
DDP
Figure 22 illustrates the operation of the SBI DROP BUS, using a negative
justification on the second to last V3 octet as an example. The justification is
indicated by asserting DPL high during the V3 octet. The timing diagram also
shows the location of one of the tributaries by asserting DV5 high during the V5
octet.
Figure 23 – DS3 DROP BUS Functional Timing
REFCLK
SSS
C1FP
SSS
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1
DDATA[7:0]
DPL
C1
H3
H3
H3
SSS
SSS
SSS
SSS
DV5
DDP
Figure 23 shows three DS-3 tributaries mapped onto the SBI bus. A negative
justification is shown for DS-3 #2 during the H3 octet with DPL asserted high. A
positive justification is shown for DS-3#1 during the first DS-3#1 octet after H3
which has DPL asserted low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
321
PMC [ PMC-SIERRA, INC ]
