PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
TDR Free Queue. TDQFI remains valid when interrupts are disabled and
may be polled to detect TDR free queue write events.
TDQRDYI:
The transmit descriptor ready queue cache read interrupt status bit
(TDQRDYI) reports transmit descriptor ready queue cache read interrupts to
the PCI host. TDQRDYI is set high when the programmable number of TDRs
is read from the TDR Ready Queue. TDQRDYI remains valid when interrupts
are disabled and may be polled to detect TDR ready queue cache read
events.
TDFQEI:
The transmit descriptor free queue error interrupt status bit (TDFQEI) reports
transmit descriptor free queue error interrupts to the PCI host. TDFQEI is set
high when an attempt to write to the transmit free queue fail due to the queue
being already full. TDFQEI bit remains valid when interrupts are disabled and
may be polled to detect TD free queue error events.
IOCI:
The transmit interrupt on complete status bit (IOCI) reports transmission
complete interrupts to the PCI host. IOCI is set high, when a packet with the
IOC bit in the TD set high is completely transmitted. IOCI remains valid when
interrupts are disabled and may be polled to detect transmission of IOC
tagged packets.
TFUDRI:
The transmit FIFO underflow error interrupt status bit (TFUDRI) reports
transmit FIFO underflow error interrupts to the PCI host. TFUDRI is set high
upon attempts to read data from the logical FIFO when it is already empty.
TFUDRI remains valid when interrupts are disabled and may be polled to
detect transmit FIFO underflow events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
97
PMC [ PMC-SIERRA, INC ]
