PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x014 : FREEDM-84P672 Master Line Loopback
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXH
Bit 16
Bit 15
R/W
Reserved
0000H
to
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
LLBEN[2]
LLBEN[1]
LLBEN[0]
0
0
0
This register controls line loopback for the three serial data links (enabled when
SPEn_EN is low).
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
LLBEN[2:0]:
The line loopback enable bits (LLBEN[2:0]) control line loopback for links #2
to #0. When LLBEN[n] is set high, the data on RD[n] is passed verbatim to
TD[n] which is then updated on the falling edge of RCLK[n]. TCLK[n] is
ignored. When LLBEN[n] is set low, TD[n] is processed normally.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
100
PMC [ PMC-SIERRA, INC ]
